An SRAM (Static Random Access Memory) memory card backed up by a battery is detachably inserted into an apparatus such as a PLC (Programmable Logic Controller). When the SRAM memory card is inserted into the apparatus and receives data from the apparatus, the SRAM memory card retains the received data for backup. In the SRAM memory card, when the voltage of the battery drops below a certain level, it is likely that a circuit such as an SRAM cannot retain the data and the data is lost. To prevent this problem, in the SRAM memory card backed up by the battery, when a battery voltage detection circuit detects the drop in the battery voltage, the battery voltage detection circuit outputs an alarm signal having an ON value to the apparatus. The apparatus urges a user to replace the battery. When the SRAM memory card vibrates, in some case, the battery instantaneously causes a connection failure and the battery voltage detection circuit detects a drop in the battery voltage by mistake and erroneously outputs an alarm signal having an ON value. To prevent the instantaneous erroneous output of the alarm signal, in the SRAM memory card backed-up by the battery, a chattering prevention circuit is provided in parallel to the battery. When chattering occurs, the chattering prevention circuit supplies a voltage to the circuit such as the SRAM on behalf of the battery.
On the other hand, Patent Literature 1 describes that, in a chattering prevention circuit, when an output of a comparator, which compares the voltage of a capacitor and a resistance-divided voltage, is inverted when an external switch is on, an NPN transistor, a base of which is connected to an output of the comparator, is turned on, and an emitter current of the NPN transistor is supplied to a base of the NPN transistor connected to both ends of the capacitor by a current mirror. Consequently, according to Patent Literature 1, because the capacitor is quickly discharged, it is possible to prevent chattering from occurring near a threshold of the capacitor.
Patent Literature 2 descries that, in a chattering removal circuit, when the potential of an input node of an inverter having a hysteresis characteristic drops from high potential to a second level, which is intermediate potential, after a switch is turned on, an output of the inverter is inverted from low potential to high potential, a transistor, a base of which is connected to an output side of the inverter, a collector of which is connected to an input node of the inverter, and an emitter of which is connected to ground potential, is turned on, and a capacitor connected to the input node of the inverter is quickly discharged. When the potential of the input node of the inverter rises from the low potential to a first level, which is intermediate potential, the output of the inverter is inverted from the high potential to the low potential, a transistor, a base of which is connected to the output side of the inverter, a collector of which is connected to the input node of the inverter, and an emitter of which is connected to power supply potential, is turned on, and the capacitor connected to the input node of the inverter is quickly charged. Consequently, according to Patent Literature 2, because the capacitor is quickly charged and discharged, even when a chattering phenomenon lasts long, the capacitor is not fully charged. It is possible to surely remove a chattering signal.
Patent Literature 3 describes that, in a power supply circuit of a small electronic device, a logical product of a battery come-off signal that changes to a “H” level when a battery comes off a power supply mounting section, an ON/OFF signal that changes to the “H” level according to an ON state of a power switch, and an output signal of a voltage detector that changes to the “H” level in a state in which a voltage supply level of a Vcc terminal reaches an operable voltage of a CPU is input to a base of a transistor, a collector of which is connected to the Vcc terminal and an emitter of which is connected to a GND terminal. Consequently, according to Patent Literature 3, when the battery comes off the power supply mounting section, accumulated charges in a capacitor in a device circuit are discharged from the Vcc terminal to the GND terminal. Therefore, the CPU does not malfunction with the accumulated charges of the capacitor. It is possible to prevent occurrence of a deficiency such as memory breakage.